 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| november 2002 1/77 rev. 2.0 ST7261 low speed usb 8-bit mcu with 3 endpoints, rom memory, lvd, wdg, timer n memories C 4k program memory (rom) with read-write protection. in-circuit programming for flash versions C 256 bytes ram memory (128-byte stack) n clock, reset and supply management C enhanced reset system (power on reset) C low voltage detector (lvd) C clock-out capability C 6 or 12 mhz oscillator (8, 4, 2, 1 mhz internal freq.) C 3 power saving modes: halt, wait and slow n usb (universal serial bus) interface C dma for low speed applications compliant with usb 1.5 mbs specification (v 1.1) and usb hid specification (v 1.0): C integrated 3.3v voltage regulator and trans- ceivers C suspend and resume operations C 3 endpoints n 11 i/o ports C 11 multifunctional bidirectional i/o lines C up to 7 external interrupts (2 vectors) C 8 high sink outputs (8ma@0.4 v/20ma@1.3) n 2 timers C configurable watchdog timer (8 to 500ms timeout) C 8-bit time base unit (tbu) for generating pe- riodic interrupts n instruction set C 8-bit data manipulation C 63 basic instructions C 17 main addressing modes C 8 x 8 unsigned multiply instruction C true bit manipulation n nested interrupts n development tools C full hardware/software development package device summary so20 pdip20 features ST72611f1 program memory - bytes 4k rom ram (stack) - bytes 256 (128) peripherals usb, watchdog, low voltage detector, time base unit i/os 11 operating supply 4.0v to 5.5v cpu frequency up to 8 mhz (with 6 or 12 mhz oscillator) operating temperature 0c to +70c packages pdip20/so20 1
table of contents 77 2/77 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pcb layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 clocks and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2 timebase unit (tbu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table of contents 77 3/77 11.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.10communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 67 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . 69 13.1 option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.2 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.1 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.2 lvd reset on vdd brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.3 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.4 to get more information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 ST7261 4/77 1 introduction the ST7261 devices are members of the st7 mi- crocontroller family designed for usb applications. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the ST7261 devices are rom versions. the flash version is supported by the st72f623f2. under software control, all devices can be placed in wait, slow, or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. general block diagram 8-bit core alu address and data bus oscin oscout reset port b usb sie port a pb7:0 (8 bits) oscillator internal clock control ram pa2:0 (3 bits) v ss v dd power supply program (4 kbytes) lvd memory watchdog usbdp usbdm usbvcc usb dma time base unit v pp (256 bytes) 1 ST7261 5/77 2 pin description figure 2. 20-pin so20 package pinout figure 3. 20-pin dip20 package pinout 14 13 12 11 15 16 17 18 oscin oscout pb7 (hs)/it8 pb6 (hs)/it7 usbvcc v dd v pp usbdp 1 2 3 4 5 6 7 8 9 10 it3/pa2 pb0 (hs)/mco pb1 (hs) pb2 (hs) pb3 (hs) pb4 (hs)/it5 reset it2/pa1 19 20 usboe/it1/pa0 v ss usbdm pb5 (hs)/it6 14 13 12 11 15 16 17 18 oscin oscout pb7 (hs)/it8 pb6 (hs)/it7 usbvcc v dd v pp usbdp 1 2 3 4 5 6 7 8 9 10 it5/pb4 (hs) mco/pb0 (hs) pb1 (hs) pb2 (hs) reset it2/pa1 19 20 usboe/it1/pa0 v ss usbdm pb5 (hs)/it6 it3/pa2 pb3 (hs) ST7261 6/77 pin description (contd) legend / abbreviations: type: i = input, o = output, s = supply input level: a = dedicated analog input input level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = high sink (on n-buffer only) port configuration capabilities: C input: float = floating, wpu = weak pull-up, int = interrupt (\ =falling edge, / =rising edge ) , ana = analog C output: od = open drain, pp = push-pull table 1. device pin description pin n pin name type level port / control main function (after reset) alternate function so20 dip20 input output input output float wpu int ana od pp 914v pp sx flash programming voltage (12v), must be tied low in user mode. 11 16 oscin these pins are used connect an external clock source to the on-chip main oscillator. 12 17 oscout 49v ss s digital ground voltage 813v dd s digital main power supply voltage 13 18 pb7/it8 i/o c t hs x \ x port b7 interrupt 8 input 14 19 pb6/it7 i/o c t hs x \ x port b6 interrupt 7 input 15 20 pb5/it6 i/o c t hs x / x port b5 interrupt 6 input 16 1 pb4/it5 i/o c t hs x / x port b4 interrupt 5 input 17 2 pb3 i/o c t hs x x port b3 18 3 pb2 i/o c t hs x x port b2 19 4 pb1 i/o c t hs x x port b1 20 5 pb0/mco i/o c t hs x x port b0 cpu clock output 1 6 pa2/it3 i/o c t x\ x port a2 interrupt 3 input 2 7 pa1/it2 i/o c t x\ x port a1 interrupt 2 input 3 8 pa0/it1/usboe i/o c t x\ x port a0 interrupt 1 input/usb output enable 10 15 reset i/o c top priority non maskable interrupt (active low) 5 10 usbdm i/o usb bidirectional data (data -) 6 11 usbdp i/o usb bidirectional data (data +) 7 12 usbvcc s usb power supply 3.3v output ST7261 7/77 pin description (contd) 2.1 pcb layout recommendation in the case of dip20 devices the user should lay- out the pcb so that the dip20 ST7261 device and the usb connector are centered on the same axis ensuring that the d- and d+ lines are of equal length. refer to figure 4 figure 4. recommended pcb layout for usb interface with dip20 package 14 13 12 11 15 16 17 18 usbvcc usbdp 1 2 3 4 5 6 7 8 9 10 19 20 usbdm usb connector ground ground ST7261 1.5kohm pull-up resistor ST7261 8/77 3 register & memory map as shown in the figure 5 , the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 64 bytes of register locations, 256 bytes of ram and 4 kbytes of user program memory. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. figure 5. memory map 0000h program memory interrupt & reset vectors hw registers 0040h 003fh (see table 2 ) ffdfh ffe0h ffffh see table 5 on page 21 0180h reserved 017fh short addressing ram zero page 017fh 0080h 00ffh (4 kbytes) f000h (128 bytes) 256 bytes ram stack or (128 bytes) efffh 16-bit addressing ram reserved 0080h 007fh ST7261 9/77 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h port a padr paddr port a data register port a data direction register 00h 00h r/w r/w 0002h 0003h port b pbdr pbddr port b data register port b data direction register 00h 00h r/w r/w. 0004h to 0007h reserved area (4 bytes) 0008h itrfre1 interrupt register 1 00h r/w 0009h misc miscellaneous register 00h r/w 000ah to 000ch reserved area (2 bytes) 000dh wdg wdgcr watchdog control register 7fh r/w 000eh to 0024h reserved area (23 bytes) 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h usb usbpidr usbdmar usbidr usbistr usbimr usbctlr usbdaddr usbep0ra usbep0rb usbep1ra usbep1rb usbep2ra usbep2rb usb pid register usb dma address register usb interrupt/dma register usb interrupt status register usb interrupt mask register usb control register usb device address register usb endpoint 0 register a usb endpoint 0 register b usb endpoint 1 register a usb endpoint 1 register b usb endpoint 2 register a usb endpoint 2 register b x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0032h to 0035h reserved area (4 bytes) 0036h 0037h tbu tbucv tbucsr tbu counter value register tbu control/status register 00h 00h r/w r/w 0038h to 003fh reserved area (8 bytes) ST7261 10/77 4 central processing unit 4.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n low power halt and wait modes n priority maskable hardware interrupts n non-maskable software/hardware interrupts 4.3 cpu registers the 6 cpu registers shown in figure 6 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 6. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value ST7261 11/77 central processing unit (contd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. its a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the bit test and branch, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt the combination of the i1 and i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 ST7261 12/77 cpu registers (contd) stack pointer (sp) read/write reset value: 017fh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 7 ). since the stack is 128 bytes deep, the 9 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 7 . C when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. C on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 7. stack manipulation example 15 8 00000001 70 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h ST7261 13/77 5 clocks and reset 5.1 clock system 5.1.1 general description the mcu accepts either a crystal or ceramic res- onator, or an external clock signal to drive the in- ternal oscillator. the internal clock (f cpu ) is de- rived from the external oscillator frequency (f osc ), by dividing by 3 and multiplying by 2. by setting the osc12/6 bit in the option byte, a 12 mhz external clock can be used giving an internal frequency of 8 mhz while maintaining a 6 mhz clock for usb (re- fer to figure 10 ). the internal clock signal (f cpu ) consists of a square wave with a duty cycle of 50%. it is further divided by 1, 2, 4 or 8 depending on the slow mode selection bits in the miscellaneous register (sms[1:0]) the internal oscillator is designed to operate with an at-cut parallel resonant quartz or ceramic res- onator in the frequency range specified for f osc . the circuit shown in figure 9 is recommended when using a crystal, and table 3 lists the recom- mended capacitors. the crystal and associated components should be mounted as close as pos- sible to the input pins in order to minimize output distortion and start-up stabilization time. table 3. recommended values for 12 mhz crystal resonator note: r smax is the equivalent serial resistor of the crystal (see crystal specification). 5.1.2 external clock input an external clock may be applied to the oscin in- put with the oscout pin not connected, as shown on figure 8 . the t oxov specifications does not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see elec- trical characteristics). 5.1.3 clock output pin (mco) the internal clock (f cpu ) can be output on port b0 by setting the mco bit in the miscellaneous regis- ter. figure 8. external clock source connections figure 9. crystal/ceramic resonator figure 10. clock block diagram r smax 20 w 25 w 70 w c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m w 1-10 m w 1-10 m w oscin oscout external clock nc oscin oscout c oscin c oscout to cpu and f cpu 8/4/2/1 mhz 6 mhz (usb) 12 or peripherals %2 0 1 osc12/6 6 mhz crystal x2 slow mode % sms[1:0] 1/2/4/8 %3 (or 4/2/1/0.5 mhz) mco pin ST7261 14/77 5.2 reset the reset procedure is used to provide an orderly software start-up or to exit low power modes. three reset modes are provided: a low voltage re- set, a watchdog reset and an external reset at the reset pin. a reset causes the reset vector to be fetched from addresses fffeh and ffffh in order to be loaded into the pc and with program execution starting from this point. an internal circuitry provides a 514 cpu clock cy- cle delay from the time that the oscillator becomes active. 5.2.1 low voltage reset low voltage reset circuitry generates a reset when v dd is: n below v it+ when v dd is rising, n below v it- when v dd is falling. during low voltage reset, the reset pin is held low, thus permitting the mcu to reset other devices. the low voltage detector can be disabled by set- ting the lvd bit of the option byte. 5.2.2 watchdog reset when a watchdog reset occurs, the r eset pin is pulled low permitting the mcu to reset other devic- es as when low voltage reset ( figure 11 ). 5.2.3 external reset the external reset is an active low input signal ap- plied to the reset pin of the mcu. as shown in figure 14 , the reset signal must stay low for a minimum of one and a half cpu clock cycles. an internal schmitt trigger at the reset pin is pro- vided to improve noise immunity. figure 11. low voltage reset functional diagram figure 12. low voltage reset signal output note : typical hysteresis (v it+ -v it- ) of 250 mv is expected figure 13. temporization timing diagram after an internal reset low voltage v dd from watchdog reset reset internal reset reset reset v dd v it+ v it- v dd addresses $fffe temporization v it+ (514 cpu clock cycles) ST7261 15/77 figure 14. reset timing diagram note: refer to electrical characteristics for values of t ddr , t oxov , v it+ and v it-. figure 15. reset block diagram note: the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). v dd oscin f cpu ffff fffe pc reset t ddr t oxov 514 cpu clock cycles delay reset r on v dd watchdog reset lvd reset internal reset pulse generator 200ns filter t w(rstl)out + 128 f osc delay ST7261 16/77 6 interrupts 6.1 introduction the st7 enhanced interrupt management pro- vides the following features: n hardware interrupts n software interrupt (trap) n nested or concurrent interrupt management with flexible interrupt priority and level management: C up to 4 software programmable nesting levels C up to 16 interrupt vectors fixed by hardware C 3 non maskable events: tli, reset, trap this interrupt management is based on: C bit 5 and bit 3 of the cpu cc register (i1:0), C interrupt software priority registers (isprx), C fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with the standard (not nest- ed) st7 interrupt controller. 6.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see table 4 ). the process- ing flow is shown in figure 16 . when an interrupt request has to be serviced: C normal processing is suspended at the end of the current instruction execution. C the pc, x, a and cc registers are saved onto the stack. C i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. C the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to interrupt mapping table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the previous level will resume. table 4. interrupt software priority levels figure 16. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 iret restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset tli pending instruction i1:0 from stack load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the interrupt stays pending than current one interrupt has a higher software priority than current one execute instruction interrupt ST7261 17/77 interrupts (contd) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: C the highest software priority interrupt is serviced, C if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 17 describes this decision process. figure 17. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and tli are non maskable and they can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, tli, trap) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 16 ). after stacking the pc, x, a and cc registers (except for reset), the corres ponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. n tli (top level hardware interrupt) this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. caution : a trap instruction must not be used in a tli service routine. n trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart in figure 16 as a tli. caution: trap can be interrupted by a tli. n reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. n external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the external interrupt control register (eicr). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically nanded. n peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the interrupt mapping table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different interrupts same highest hardware priority serviced priority highest software priority serviced ST7261 18/77 interrupts (contd) 6.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit from the halt modes (see column exit from halt in interrupt mapping table). when several pending interrupts are present while exit- ing halt mode, the first one serviced can only be an interrupt with exit from halt mode capability and it is selected through the same decision proc- ess shown in figure 17 . note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 6.4 concurrent & nested management the following figure 18 and figure 19 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 19 . the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 18. concurrent interrupt management figure 19. nested interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes ST7261 19/77 interrupts (contd) 6.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see interrupt dedicated instruction set table). *note : tli, trap and reset events are non maskable sources and can interrupt a level 3 pro- gram. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset value: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. C each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. C each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. C level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and tli vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-fff8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits ST7261 20/77 6.6 interrupt register interrupt register 1 (itrfre1) address: 0008h - read/write reset value: 0000 0000 (00h) bit 7:0 = itie interrupt enable 0: i/o pin free for general purpose i/o 1: iti external interrupt enabled. note: the corresponding interrupt is generated when: C a rising edge occurs on the it5/it6 pins C a falling edge occurs on the it1, 2, 3, 4, 7 and 8 pins interrupt register 2 (itrfre2) address: 0039h - read/write reset value: 0000 0000 (00h) bit 7:6 = ctl[3:2] it[12:11] interrupt sensitivity these bits are set and cleared by software. they are used to configure the edge and level sensitivity of the it12 and it11 external interrupt pins (this means that both must have the same sensitivity). bit 5:4 = ctl[1:0] it[10:9]1nterrupt sensitivity these bits are set and cleared by software. they are used to configure the edge and level sensitivity of the it10 and it9 external interrupt pins (this means that both must have the same sensitivity). bit 3:0 = itie interrupt enable 0: i/o pin free for general purpose i/o 1: iti external interrupt enabled. 70 it8e it7e it6e it5e it4e it3e it2e it1e 70 ctl3 ctl2 ctl1 ctl0 it12e it11e it10e it9e ctl3 ctl2 it[12:11] sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge ctl1 ctl0 it[10:9] sensitivity 0 0 falling edge and low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge ST7261 21/77 interrupts (contd) table 5. interrupt mapping table 6. nested interrupts register map and reset values n source block description register label exit from halt address vector priority order reset vector yes fffeh-ffffh highest priority lowest priority trap software interrupt vector no fffch-fffdh 0 not used fffah-fffbh 1 usb usb end suspend interrupt vector usbistr yes fff8h-fff9h 2 i/o ports port a external interrupts it[3:1] itrfre1 yes fff6h-fff7h 3 port b external interrupts it[8:5] yes fff4h-fff5h 4 not used fff2h-fff3h 5 tbu timebase unit interrupt vector tbucsr no fff0h-fff1h 6 not used ffeeh-ffefh 7 not used ffech-ffedh 8 not used ffeah-ffebh 9 usb usb interrupt vector usbistr no ffe8h-ffe9h 10 not used ffe6h-ffe7h address (hex.) register label 76543210 0032h ispr0 reset value ext. interrupt port b ext. interrupt port a usb end susp not used i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0033h ispr1 reset value spi art tbu ext. interrupt port c i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0034h ispr2 reset value not used adc usb sci i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0035h ispr3 reset value1111 not used not used i1_13 1 i0_13 1 i1_12 1 i0_12 1 ST7261 22/77 7 power saving modes 7.1 introduction there are three power saving modes. slow mode is selected by setting the sms bits in the miscella- neous register. wait and halt modes may be en- tered using the wfi and halt instructions. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 3 and multi- plied by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the oscillator status. 7.1.1 slow mode in slow mode, the oscillator frequency can be di- vided by a value defined in the miscellaneous register. the cpu and peripherals are clocked at this lower frequency. slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage. 7.2 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the wfi st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0, to enable all interrupts. all other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 20 . figure 20. wait mode flow chart wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 514 cpu clock cycles delay if reset note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped. ST7261 23/77 power saving modes (contd) 7.3 halt mode the halt mode is the mcu lowest power con- sumption mode. the halt mode is entered by ex- ecuting the halt instruction. the internal oscilla- tor is then turned off, causing all internal process- ing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the condi- tion code register is cleared. thus, any of the ex- ternal interrupts (iti or usb end suspend mode), are allowed and if an interrupt occurs, the cpu clock becomes active. the mcu can exit halt mode on reception of ei- ther an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, or a reset. the oscillator is then turned on and a stabi- lization time is provided before releasing cpu op- eration. the stabilization time is 514 cpu clock cy- cles. after the start up delay, the cpu continues opera- tion by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. figure 21. halt mode flow chart n n external interrupt* reset halt instruction 514 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the inter- rupt routine and cleared when the cc register is popped. ST7261 24/77 8 i/o ports 8.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: C analog signal input (adc) C alternate signal input/output for the on-chip pe- ripherals. C external interrupt generation an i/o port is composed of up to 8 pins. each pin can be programmed independently as digital input or digital output. 8.2 functional description each port is associated with 2 main registers: C data register (dr) C data direction register (ddr) each i/o pin may be programmed using the corre- sponding register bits in ddr register: bit x corre- sponding to pin x of the port. the same corre- spondence is used for the dr register. table 7. i/o pin functions 8.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. notes : 1. all the inputs are triggered by a schmitt trigger. 2. when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is configured as an output. interrupt function when an external interrupt function of an i/o pin, is enabled using the itfre registers, an event on this i/o can generate an external interrupt request to the cpu. the interrupt sensitivity is programma- ble, the options are given in the description of the itrfre interrupt registers. each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupts sec- tion). if more than one input pin is selected simul- taneously as interrupt source, this is logically an- ded and inverted. for this reason, if an event oc- curs on one of the interrupt pins, it masks the other ones. 8.2.2 output mode the pin is configured in output mode by setting the corresponding ddr register bit (see table 7). in this mode, writing 0 or 1 to the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. note : in this mode, the interrupt function is disa- bled. 8.2.3 alternate functions digital alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. notes: 1. input pull-up configuration can cause an unex- pected value at the alternate peripheral input. 2. when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). warning : alternate functions of peripherals must must not be activated when the external interrupts are enabled on the same pin, in order to avoid generating spurious interrupts. ddr mode 0 input 1 output ST7261 25/77 i/o ports (contd) analog alternate functions when the pin is used as an adc input, the i/o must be configured as input. the analog multiplex- er (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maximum ratings. 8.2.4 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr register and spe- cific features of the i/o port such as adc input or true open drain. ST7261 26/77 i/o ports (contd) 8.2.5 port a table 8. port a description figure 22. pa[2:0] configuration port a i/o alternate function input* output signal condition pa0 floating push-pull usboe usboe = 1 (misc) it1 schmitt triggered input it1e = 1 (itrfre1) pa1 floating push-pull it2 schmitt triggered input it2e = 1 (itrfre1) pa2 floating push-pull it3 schmitt triggered input it3e = 1 (itrfre1) *reset state dr ddr latch latch dr sel ddr sel v dd pad alternate enable alternate enable digital enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 v ss data bus v dd diodes ST7261 27/77 i/o ports (contd) 8.2.6 port b table 9. port b description figure 23. port b configuration port b i/o alternate function input* output signal condition pb0 floating push-pull (high sink) mco (main clock output) mco = 1 (miscr) pb1 floating push-pull (high sink) pb2 floating push-pull (high sink) pb3 floating push-pull (high sink) pb4 floating push-pull (high sink) it5 schmitt triggered input it5e = 1 (itrfre1) pb5 floating push-pull (high sink) it6 schmitt triggered input it6e = 1 (itrfre1) pb6 floating push-pull (high sink) it7 schmitt triggered input it7e = 1 (itrfre1) pb7 floating push-pull (high sink) it8 schmitt triggered input it8e = 1 (itrfre1) *reset state dr ddr latch latch dr sel ddr sel v dd pad alternate enable alternate enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd diodes data bus ST7261 28/77 i/o ports (contd) 8.2.7 register description data register (dr) port x data register pxdr with x = a or b. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a or b. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 ST7261 29/77 i/o ports (contd) table 10. i/o port register map and reset values address (hex.) register label 76543210 reset value of all i/o port registers 00000000 0000h padr msb lsb 0001h paddr 0002h pbdr msb lsb 0003h pbddr ST7261 30/77 8.3 miscellaneous register miscellaneous register read write reset value - 0000 0000 (00h) bits 7:4 = reserved bits 3:2 = sms[1:0] slow mode selection these bits select the slow mode frequency (de- pending on the oscillator frequency configured by option byte). bit 1 = usboe usb output enable 0: pa0 port free for general purpose i/o 1: usboe alternate function enabled. the usb output enable signal is output on the pa0 port (at 1 when the st7 usb is transmitting data). bit 0 = mco main clock out 0: pb0 port free for general purpose i/o 1: mco alternate function enabled (f cpu output on pb0 i/o port) 70 - - - - sms1 sms0 us- boe mco osc12/6 sms1 sms0 slow mode frequency (mhz.) f osc = 6 mhz. 00 4 01 2 10 1 1 1 0.5 f osc = 12 mhz. 00 8 01 4 10 2 11 1 ST7261 31/77 9 on-chip peripherals 9.1 watchdog timer (wdg) 9.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counters contents before the t6 bit be- comes cleared. 9.1.2 main features n programmable timer (64 increments of 65536 cpu cycles) n programmable reset n reset (if watchdog activated) when the t6 bit reaches zero n hardware watchdog selectable by option byte 9.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 65,536 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 11 ): C the wdga bit is set (watchdog enabled) C the t6 bit is set to prevent generating an imme- diate reset C the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 11.watchdog timing (f cpu = 8 mhz) figure 24. watchdog block diagram cr register initial value wdg timeout period (ms) max ffh 524.288 min c0h 8.192 reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) ? 65536 t1 t2 t3 t4 t5 ST7261 32/77 watchdog timer (contd) 9.1.4 software watchdog option if software watchdog is selected by option byte, the watchdog is disabled following a reset. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). 9.1.5 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. 9.1.6 low power modes wait instruction no effect on watchdog. halt instruction halt mode can be used when the watchdog is en- abled. when the oscillator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg re- starts counting after 514 cpu clocks. in the case of the software watchdog option, if a reset is gen- erated, the wdg is disabled (reset state). recommendations C make sure that an external event is available to wake up the microcontroller from halt mode. C before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcon- troller. C when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as input before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. C the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. C as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 9.1.7 interrupts none. 9.1.8 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 12. watchdog timer register map and reset values 70 wdga t6 t5 t4 t3 t2 t1 t0 address (hex.) register label 76543210 0dh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 ST7261 33/77 9.2 timebase unit (tbu) 9.2.1 introduction the timebase unit (tbu) can be used to generate periodic interrupts. 9.2.2 main features n 8-bit upcounter n programmable prescaler n period between interrupts: max. 8.1ms (at 8 mhz f cpu ) n maskable interrupt 9.2.3 functional description the tbu operates as a free-running upcounter. when the tcen bit in the tbucsr register is set by software, counting starts at the current value of the tbucv register. the tbucv register is incre- mented at the clock rate output from the prescaler selected by programming the pr[2:0] bits in the tbucsr register. when the counter rolls over from ffh to 00h, the ovf bit is set and an interrupt request is generat- ed if ite is set. the user can write a value at any time in the tbucv register. 9.2.4 programming example in this example, timer is required to generate an in- terrupt after a delay of 1 ms. assuming that f cpu is 8 mhz and a prescaler divi- sion factor of 256 will be programmed using the pr[2:0] bits in the tbucsr register, 1 ms = 32 tbu timer ticks. in this case, the initial value to be loaded in the tbucv must be (256-32) = 224 (e0h). ld a, e0h ld tbucv, a ; initialize counter value ld a 1fh ; ld tbucsr, a ; prescaler factor = 256, ; interrupt enable, ; tbu enable figure 25. tbu block diagram tbu 8-bit upcounter (tbucv register) interrupt request tbu prescaler f cpu tbucsr register pr1 pr0 pr2 tcen ite ovf msb lsb 0 0 ST7261 34/77 timebase unit (contd) 9.2.5 low power modes 9.2.6 interrupts note : the ovf interrupt event is connected to an interrupt vector (see interrupts chapter). it generates an interrupt if the ite bit is set in the tbucsr register and the i-bit in the cc register is reset (rim instruction). 9.2.7 register description tbu counter value register (tbucv) read/write reset value: 0000 0000 (00h) bit 7:0 = cv[7:0] counter value this register contains the 8-bit counter value which can be read and written anytime by soft- ware. it is continuously incremented by hardware if tcen=1. tbu control/status register (tbucsr) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved must be kept cleared. bit 5 = ovf overflow flag this bit is set only by hardware, when the counter value rolls over from ffh to 00h. it is cleared by software reading the tbucsr register. writing to this bit does not change the bit value. 0: no overflow 1: counter overflow bit 4 = ite interrupt enabled. this bit is set and cleared by software. 0: overflow interrupt disabled 1: overflow interrupt enabled. an interrupt request is generated when ovf=1. bit 3 = tcen tbu enable. this bit is set and cleared by software. 0: tbu counter is frozen and the prescaler is reset. 1: tbu counter and prescaler running. bit 2:0 = pr[2:0] prescaler selection these bits are set and cleared by software to se- lect the prescaling factor. mode description wait no effect on tbu halt tbu halted. interrupt event event flag enable control bit exit from wait exit from halt counter over- flow event ovf ite yes no 70 cv7 cv6 cv5 cv4 cv3 cv2 cv1 cv0 70 0 0 ovf ite tcen pr2 pr1 pr0 pr2 pr1 pr0 prescaler division factor 000 2 001 4 011 8 100 16 101 32 101 64 110 128 111 256 ST7261 35/77 timebase unit (contd) table 13. tbu register map and reset values address (hex.) register label 76543210 0036h tbucv reset value cv7 0 cv6 0 cv5 0 cv4 0 cv3 0 cv2 0 cv1 0 cv0 0 0037h tbusr reset value - 0 - 0 ovf 0 ite 0 tcen 0 pr2 0 pr1 0 pr0 0 ST7261 36/77 9.3 usb interface (usb) 9.3.1 introduction the usb interface implements a low-speed func- tion interface between the usb and the st7 mi- crocontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and dma. no external components are needed apart from the external pull-up on usbdm for low speed recognition by the usb host. the use of dma architecture allows the endpoint definition to be completely flexible. endpoints can be config- ured by software as in or out. 9.3.2 main features n usb specification version 1.1 compliant n supports low-speed usb protocol n two or three endpoints (including default one) depending on the device (see device feature list and register map) n crc generation/checking, nrzi encoding/ decoding and bit-stuffing n usb suspend/resume operations n dma data transfers n on-chip 3.3v regulator n on-chip usb transceiver 9.3.3 functional description the block diagram in figure 26 , gives an overview of the usb interface hardware. for general information on the usb, refer to the universal serial bus specifications document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmis- sion/reception, and handshaking as required by the usb standard. it also performs frame format- ting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontrol- ler is ready to transmit/receive, and how many bytes need to be transmitted. dma when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place, using dma. at the end of the transaction, an interrupt is generated. interrupts by reading the interrupt status register, applica- tion software can know which usb event has oc- curred. figure 26. usb block diagram cpu memory transceiver 3.3v voltage regulator sie endpoint dma interrupt address, and interrupts usbdm usbdp usbvcc 6 mhz registers registers data buses usbgnd ST7261 37/77 usb interface (contd) 9.3.4 register description dma address register (dmar) read / write reset value: undefined bits 7:0= da[15:8] dma address bits 15-8. software must write the start address of the dma memory area whose most significant bits are given by da15-da6. the remaining 6 address bits are set by hardware. see the description of the idr register and figure 27 . interrupt/dma register (idr) read / write reset value: xxxx 0000 (x0h) bits 7:6 = da[7:6] dma address bits 7-6. software must reset these bits. see the descrip- tion of the dmar register and figure 27 . bits 5:4 = ep[1:0] endpoint number (read-only). these bits identify the endpoint which required at- tention. 00: endpoint 0 01: endpoint 1 10: endpoint 2 when a ctr interrupt occurs (see register istr) the software should read the ep bits to identify the endpoint which has sent or received a packet. bits 3:0 = cnt[3:0] byte count (read only). this field shows how many data bytes have been received during the last data reception. note: not valid for data transmission. figure 27. dma buffers 70 da15 da14 da13 da12 da11 da10 da9 da8 70 da7 da6 ep1 ep0 cnt3 cnt2 cnt1 cnt0 endpoint 0 rx endpoint 0 tx endpoint 2 rx endpoint 1 tx 000000 000111 001000 001111 010000 010111 011000 011111 da15-6,000000 endpoint 1 rx endpoint 2 tx 100000 100111 101000 101111 ST7261 38/77 usb interface (contd) pid register (pidr) read only reset value: xx00 0000 (x0h) bits 7:6 = tp[3:2] token pid bits 3 & 2 . usb token pids are encoded in four bits. tp[3:2] correspond to the variable token pid bits 3 & 2. note: pid bits 1 & 0 have a fixed value of 01. when a ctr interrupt occurs (see register istr) the software should read the tp3 and tp2 bits to retrieve the pid name of the token received. the usb standard defines tp bits as: bits 5:3 reserved. forced by hardware to 0. bit 2 = rx_sez received single-ended zero this bit indicates the status of the rx_sez trans- ceiver output. 0: no se0 (single-ended zero) state 1: usb lines are in se0 (single-ended zero) state bit 1 = rxd received data 0: no k-state 1: usb lines are in k-state this bit indicates the status of the rxd transceiver output (differential receiver output). note: if the environment is noisy, the rx_sez and rxd bits can be used to secure the application. by interpreting the status, software can distinguish a valid end suspend event from a spurious wake-up due to noise on the external usb line. a valid end suspend is followed by a resume or reset se- quence. a resume is indicated by rxd=1, a re- set is indicated by rx_sez=1. bit 0 = reserved. forced by hardware to 0. interrupt status register (istr) read / write reset value: 0000 0000 (00h) when an interrupt occurs these bits are set by hardware. software must read them to determine the interrupt type and clear them after servicing. note: these bits cannot be set by software. bit 7 = susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb bus. the suspend request check is active immedi- ately after each usb reset event and its disabled by hardware when suspend mode is forced (fsusp bit of ctlr register) until the end of resume sequence. bit 6 = dovr dma over/underrun . this bit is set by hardware if the st7 processor cant answer a dma request in time. 0: no over/underrun detected 1: over/underrun detected bit 5 = ctr correct transfer. this bit is set by hardware when a correct transfer operation is per- formed. the type of transfer can be determined by looking at bits tp3-tp2 in register pidr. the end- point on which the transfer was made is identified by bits ep1-ep0 in register idr. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack handshakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. bit 4 = err error. this bit is set by hardware whenever one of the er- rors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing or nonstandard framing error detected 70 tp3tp2000 rx_ sez rxd 0 tp3 tp2 pid name 00 out 10 in 1 1 setup 70 susp dovr ctr err iovr esusp reset sof ST7261 39/77 usb interface (contd) bit 3 = iovr interrupt overrun. this bit is set when hardware tries to set err, or sof before they have been cleared by software. 0: no overrun detected 1: overrun detected bit 2 = esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb in- terface up from suspend mode. this interrupt is serviced by a specific vector, in or- der to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected bit 1 = reset usb reset. this bit is set by hardware when the usb reset se- quence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0ra, ep0rb, ep1ra, ep1rb, ep2ra and ep2rb registers are reset by a usb reset. bit 0 = sof start of frame. this bit is set by hardware when a low-speed sof indication (keep-alive strobe) is seen on the usb bus. it is also issued at the end of a resume se- quence. 0: no sof signal detected 1: sof signal detected note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruc- tion where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read- modify-write instructions like and , xor.. interrupt mask register (imr) read / write reset value: 0000 0000 (00h) bits 7:0 = these bits are mask bits for all interrupt condition bits included in the istr. whenever one of the imr bits is set, if the corresponding istr bit is set, and the i bit in the cc register is cleared, an interrupt request is generated. for an explanation of each bit, please refer to the corresponding bit description in istr. control register (ctlr) read / write reset value: 0000 0110 (06h) bits 7:4 = reserved. forced by hardware to 0. bit 3 = resume resume . this bit is set by software to wake-up the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. bit 2 = pdwn power down . this bit is set by software to turn off the 3.3v on- chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, soft- ware should allow at least 3 s for stabilisation of the power supply before using the usb interface. bit 1 = fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be halted allowing at least 600 ns before issuing the halt instruction. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it resets this bit (it can also be reset by software). bit 0 = fres force reset. this bit is set by software to force a reset of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb is held in reset state until software clears this bit, at which point a usb-reset in- terrupt will be generated if enabled. 70 sus pm dov rm ctr m err m iovr m esu spm res etm sof m 70 0 0 0 0 resume pdwn fsusp fres ST7261 40/77 usb interface (contd) device address register (daddr) read / write reset value: 0000 0000 (00h) bit 7 = reserved. forced by hardware to 0. bits 6:0 = add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received from the usb bus or forced through bit fres in the ctlr register. endpoint n register a (epnra) read / write reset value: 0000 xxxx (0xh) these registers ( ep0ra , ep1ra and ep2ra ) are used for controlling data transmission. they are also reset by the usb bus reset. note : endpoint 2 and the ep2ra register are not available on some devices (see device feature list and register map). bit 7 = st_out status out. this bit is set by software to indicate that a status out packet is expected: in this case, all nonzero out data transfers on the endpoint are stalled instead of being acked. when st_out is reset, out transactions can have any number of bytes, as needed. bit 6 = dtog_tx data toggle, for transmission transfers. it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware at the re- ception of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dtog_rx (see epnrb) are normally updated by hardware, at the receipt of a relevant pid. they can be also written by software. bits 5:4 = stat_tx[1:0] status bits, for transmis- sion transfers. these bits contain the information about the end- point status, which are listed below: these bits are written by software. hardware sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) related to a in or setup transaction addressed to this endpoint; this allows the software to prepare the next set of data to be transmitted. bits 3:0 = tbc[3:0] transmit byte count for end- point n. before transmission, after filling the transmit buff- er, software must write in the tbc field the trans- mit packet size expressed in bytes (in the range 0- 8). warning: any value outside the range 0-8 will- induce undesired effects (such as continuous data transmission). 70 0 add6 add5 add4 add3 add2 add1 add0 70 st_ out dtog _tx stat _tx1 stat _tx0 tbc 3 tbc 2 tbc 1 tbc 0 stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is ena- bled for transmission. ST7261 41/77 usb interface (contd) endpoint n register b (epnrb) read / write reset value: 0000 xxxx (0xh) these registers ( ep1rb and ep2rb ) are used for controlling data reception on endpoints 1 and 2. they are also reset by the usb bus reset. note : endpoint 2 and the ep2rb register are not available on some devices (see device feature list and register map). bit 7 = ctrl control. this bit should be 0. note: if this bit is 1, the endpoint is a control end- point. (endpoint 0 is always a control endpoint, but it is possible to have more than one control end- point). bit 6 = dtog_rx data toggle, for reception trans- fers . it contains the expected value of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by hardware in the first stage (setup stage) of a control transfer (setup trans- actions start always with data0 pid). the receiv- er toggles dtog_rx only if it receives a correct data packet and the packets data pid matches the receiver sequence bit. bits 5:4 = stat_rx [1:0] status bits, for reception transfers. these bits contain the information about the end- point status, which are listed below: these bits are written by software. hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) related to an out or set- up transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. bits 3:0 = ea[3:0] endpoint address . software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. usually ep1rb contains 0001 and ep2rb contains 0010. endpoint 0 register b (ep0rb) read / write reset value: 1000 0000 (80h) this register is used for controlling data reception on endpoint 0. it is also reset by the usb bus re- set. bit 7 = forced by hardware to 1. bits 6:4 = refer to the epnrb register for a de- scription of these bits. bits 3:0 = forced by hardware to 0. 70 ctrl dtog _rx stat _rx1 stat _rx0 ea3 ea2 ea1 ea0 stat_rx1 stat_rx0 meaning 00 disabled : reception transfers cannot be exe- cuted. 01 stall: the endpoint is stalled and all reception requests result in a stall handshake. 10 nak : the endpoint is na- ked and all reception re- quests result in a nak handshake. 11 valid : this endpoint is enabled for reception. 70 1 dtog rx stat rx1 stat rx0 0000 stat_rx1 stat_rx0 meaning ST7261 42/77 usb interface (contd) 9.3.5 programming considerations the interaction between the usb interface and the application program is described below. apart from system reset, action is always initiated by the usb interface, driven by one of the usb events associated with the interrupt status register (is- tr) bits. 9.3.5.1 initializing the registers at system reset, the software must initialize all reg- isters to enable the usb interface to properly gen- erate interrupts and dma requests. 1. initialize the dmar, idr, and imr registers (choice of enabled interrupts, address of dma buffers). refer the paragraph titled initializing the dma buffers. 2. initialize the ep0ra and ep0rb registers to enable accesses to address 0 and endpoint 0 to support usb enumeration. refer to the para- graph titled endpoint initialization. 3. when addresses are received through this channel, update the content of the daddr. 4. if needed, write the endpoint numbers in the ea fields in the ep1rb and ep2rb register. 9.3.5.2 initializing dma buffers the dma buffers are a contiguous zone of memo- ry whose maximum size is 48 bytes. they can be placed anywhere in the memory space to enable the reception of messages. the 10 most signifi- cant bits of the start of this memory area are spec- ified by bits da15-da6 in registers dmar and idr, the remaining bits are 0. the memory map is shown in figure 27 . each buffer is filled starting from the bottom (last 3 address bits=000) up. 9.3.5.3 endpoint initialization to be ready to receive: set stat_rx to valid (11b) in ep0rb to enable reception. to be ready to transmit: 1. write the data in the dma transmit buffer. 2. in register epnra, specify the number of bytes to be transmitted in the tbc field 3. enable the endpoint by setting the stat_tx bits to valid (11b) in epnra. note: once transmission and/or reception are en- abled, registers epnra and/or epnrb (respec- tively) must not be modified by software, as the hardware can change their value on the fly. when the operation is completed, they can be ac- cessed again to enable a new operation. 9.3.5.4 interrupt handling start of frame (sof) the interrupt service routine may monitor the sof events for a 1 ms synchronization event to the usb bus. this interrupt is generated at the end of a resume sequence and can also be used to de- tect this event. usb reset (r eset) when this event occurs, the daddr register is re- set, and communication is disabled in all endpoint registers (the usb interface will not respond to any packet). software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. to do this, set the stat_rx bits in the ep0rb register to valid. suspend (susp) the cpu is warned about the lack of bus activity for more than 3 ms, which is a suspend request. the software should set the usb interface to sus- pend mode and execute an st7 halt instruction to meet the usb-specified power constraints. end suspend (esusp) the cpu is alerted by activity on the usb, which causes an esusp interrupt. the st7 automatical- ly terminates halt mode. correct transfer (ctr) 1. when this event occurs, the hardware automat- ically sets the stat_tx or stat_rx to nak. note: every valid endpoint is naked until soft- ware clears the ctr bit in the istr register, independently of the endpoint number addressed by the transfer which generated the ctr interrupt. note: if the event triggering the ctr interrupt is a setup transaction, both stat_tx and stat_rx are set to nak. 2. read the pidr to obtain the token and the idr to get the endpoint number related to the last transfer. note: when a ctr interrupt occurs, the tp3- tp2 bits in the pidr register and ep1-ep0 bits in the idr register stay unchanged until the ctr bit in the istr register is cleared. 3. clear the ctr bit in the istr register. ST7261 43/77 usb interface (contd) table 14. usb register map and reset values address (hex.) register name 7 6 5 4 3210 25 pidr reset value tp3 x tp2 x 0 0 0 0 0 0 rx_sez 0 rxd 0 0 0 26 dmar reset value da15 x da14 x da13 x da12 x da11 x da10 x da9 x da8 x 27 idr reset value da7 x da6 x ep1 x ep0 x cnt3 0 cnt2 0 cnt1 0 cnt0 0 28 istr reset value susp 0 dovr 0 ctr 0 err 0 iovr 0 esusp 0 reset 0 sof 0 29 imr reset value suspm 0 dovrm 0 ctrm 0 errm 0 iovrm 0 esuspm 0 resetm 0 sofm 0 2a ctlr reset value 0 0 0 0 0 0 0 0 resume 0 pdwn 1 fsusp 1 fres 0 2b daddr reset value 0 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 2c ep0ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2d ep0rb reset value 1 1 dtog_rx 0 stat_rx1 0 stat_rx0 0 0 0 0 0 0 0 0 0 2e ep1ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2f ep1rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x 30 ep2ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 31 ep2rb reset value ctrl 0 dtog_rx 0 stat_rx1 0 stat_rx0 0 ea3 x ea2 x ea1 x ea0 x ST7261 44/77 10 instruction set 10.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: C long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. C short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 15. st7 addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 ST7261 45/77 instruction set overview (contd) 10.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 10.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 10.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 10.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 10.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations ST7261 46/77 instruction set overview (contd) 10.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 16. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 10.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative ST7261 47/77 instruction set overview (contd) 10.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf ST7261 48/77 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > ST7261 49/77 instruction set overview (contd) mnemo description function/example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z ST7261 50/77 11 electrical characteristics 11.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 11.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 s ). 11.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v. they are given only as de- sign guidelines and are not tested. 11.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 11.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 28 . figure 28. pin loading conditions 11.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 29 . figure 29. pin input voltage c l st7 pin v in st7 pin ST7261 51/77 11.2 absolute maximum ratings stresses above those listed as absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 11.2.1 voltage characteristics 11.2.2 current characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset , 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in ST7261 53/77 11.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). note 1: typical data are based on t a =25c and not tested in production note 2: data based on design simulation, not tested in production. note 3: usb transceiver is powered down. note 4: low voltage reset function enabled. cpu in halt mode. current consumption of external pull-up (1.5kohms to usbvcc) and pull-down (15kohms to v ssa ) not included. figure 31. typ. i dd in run at 4 and 8 mhz f cpu figure 32. typ. i dd in wait at 4 and 8 mhz f cpu symbol parameter conditions typ 1) max unit d i dd( d ta) supply current variation vs. temperature constant v dd and f cpu 10 % i dd cpu run mode i/os in input mode. usb transceiver and lvd disabled f cpu = 4 mhz 4 6 ma f cpu = 8 mhz 6 12 lvd enabled. usb in transmission 2) f cpu = 4 mhz 10 14 ma f cpu = 8 mhz 12 20 ma cpu wait mode 2) i/os in input mode. usb transceiver and lvd disabled f cpu = 8 mhz 4.5 8 ma lvd enabled. usb in transmission f cpu = 8 mhz 11 18 ma cpu halt mode 3) with lvd 4) 130 200 m a without lvd 30 50 usb suspend mode 4) 130 200 m a 1 2 3 4 5 6 7 8 3 3.5 4 4.5 5 5.5 6 vdd (v) idd (ma) idd run at fcpu=8mhz idd run at fcpu=4mhz 0 1 2 3 4 5 6 3456 vdd (v) idd (ma) idd wait at fcpu=4mhz idd wait at fcpu=8mhz ST7261 54/77 11.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . 11.5.1 general timings 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 11.5.2 control timing characteristics note 1: not tested in production, guaranteed by design. symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time f cpu =8mhz 2 3 12 t cpu 250 375 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) + 10 t cpu f cpu =8mhz 10 22 t cpu 1.25 2.75 m s control timings symbol parameter conditions value unit min 1) typ. 1) max 1) f osc oscillator frequency 12 mhz f cpu operating frequency 8 mhz t rl external reset input pulse width 1.5 t cpu t porl internal power reset duration 514 t cpu t rstl reset pin output pulse width 10 s t wdg watchdog time-out f cpu = 8mhz 65536 8.192 4194304 524.288 t cpu ms t oxov crystal oscillator start-up time 20 30 40 ms t ddr power up rise time from v dd = 0 to 4v 100 ms ST7261 55/77 clock and timing characteristics (contd) 11.5.3 external clock source note 1: data based on design simulation and/or technology characteristics, not tested in production figure 33. typical application with an external clock source figure 34. typical application with a crystal resonator symbol parameter conditions min typ max unit v oscinh oscin input pin high level voltage see figure 33 0.7xv dd v dd v v oscinl oscin input pin low level voltage v ss 0.3xv dd t w(oscinh) t w(oscinl) oscin high or low time 1) 15 ns t r(oscin) t f(oscin) oscin rise or fall time 1) 15 i l oscx input leakage current v ss v in v dd 1 m a oscin oscout f osc external st72xxx clock source not connected internally v oscinl v oscinh t r(oscin) t f(oscin) t w(oscinh) t w(oscinl) i l 90% 10% oscout oscin f osc c l1 c l2 i 2 r f st72xxx resonator ST7261 56/77 11.6 memory characteristics subject to general operating conditions for f cpu , and t a unless otherwise specified. 11.6.1 ram and hardware registers note 1: guaranteed by design. not tested in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 2.0 v ST7261 57/77 11.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 11.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). n esd: electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 35. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested 10nf and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance trade-off. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter conditions neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 0.7 0.7 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 11 v dd v ss 0.1 m f 10nf v dd st72xxx v ssa v dda 0.1 m f power supply source st7 digital noise filtering external noise filtering ST7261 58/77 emc characteristics (contd) 11.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 11.7.2.1 electro-static discharge (esd) electro-static discharges (1 positive then 1 nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). the human body model is simulated. this test conforms to the jesd22-a114a stand- ard. see figure 36 and the following test sequenc- es. human body model test sequence C c l is loaded through s1 by the hv pulse gener- ator. C s1 switches position from generator to r. C a discharge from c l through r (body resistance) to the st7 occurs. C s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. 11.7.2.2 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: C corrupted program counter C unexpected reset C critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device,over the range of spec- ification values.when unexpected behaviour is de- tected, the sofware can be hardened to prevent unrecoverable errors occurring (see application note an1015). absolute maximum ratings figure 36. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator human body model ST7261 59/77 emc characteristics (contd) 11.7.2.3 static and dynamic latch-up n lu: 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu: electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 37 . for more details, refer to the an1181 st7 application note. electrical sensitivities figure 37. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a r ch =50m w r d =330 w c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st7 v dd v ss ST7261 60/77 emc characteristics (contd) 11.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 38 and figure 39 for standard pins and in figure 40 and figure 41 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: C a diode to v dd (3a) and a diode from v ss (3b) C a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: C a resistor in series with the pad (1) C a diode to v dd (2a) and a diode from v ss (2b) C a protection device between v dd and v ss (4) figure 38. positive stress on a standard pad vs. v ss figure 39. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path ST7261 61/77 emc characteristics (contd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completely absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss , v ssa , ...) and power supply (v dd , v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 42 is implemented to protect the device against esd. figure 40. positive stress on a true open drain pad vs. v ss figure 41. negative stress on a true open drain pad vs. v dd figure 42. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v dda v ssa v dda v dd v ss back to back diode between grounds v ssa ST7261 62/77 11.8 i/o port pin characteristics 11.8.1 general characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v, not tested in production. 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 43 ). data based on design simulation and/or technology characteristics, not tested in production. 3. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. figure 43. two typical applications with unused i/o pin symbol parameter conditions min typ 1) max unit v il input low level voltage 0.3xv dd v v ih input high level voltage 0.7xv dd v in input voltage true open drain i/o pins v ss 6.0 v other i/o pins v dd v hys schmitt trigger voltage hysteresis 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 2) floating input mode 200 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 25 t w(it)in external interrupt pulse time 3) 1t cpu 10k w unused i/o port st72xxx 10k w unused i/o port st72xxx v dd ST7261 63/77 i/o port pin characteristics (contd) 11.8.2 output driving current subject to general operating condition for v dd , f cpu , and t a unless otherwise specified. figure 44. typ. v ol at v dd =5v (std. port) figure 45. typ. v ol at v dd =5v (high-sink) figure 46. typ. v dd -v oh at v dd =5v (std. port) figure 47. typ. v dd -v oh at v dd =5v (high-sink) notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 11.2 and the sum of i io (i/ o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 11.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin when up to 8 pins are sunk at same time (see figure 44 ) v dd =5v i io =+5ma 1.3 v i io =+2ma 0.4 output low level voltage for a high sink i/o pin when up to4 pins are sunk at same time (see figure 45 ) i io =+20ma 1.3 i io =+8ma 0.4 v oh 2) output high level voltage for an i/o pin when up to 8 pins are sourced at same time (see figure 46 ) i io =-5ma v dd -2.0 i io =-2ma v dd -0.8 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 0246810 lio(ma) vol (v) at ta=25c 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 0 5 10 15 lio (ma) vol (v) at 25c 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 -8 -7 -6 -5 -4 -3 -2 -1 0 lio (ma) vdd-voh (v) at ta=25c 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -8 -7 -6 -5 -4 -3 -2 -1 0 lio (ma) vdd-voh (v) at ta=25c ST7261 64/77 i/o port pin characteristics (contd) figure 48. typical v ol vs. v dd (standard port) figure 49. typical v ol vs. v dd (high-sink port) figure 50. typical v dd -v oh vs. v dd (standard port) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 3456 vdd(v) vol(v) at lio=2m a 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at lio=5ma 0.00 0.05 0.10 0.15 0.20 0.25 0.30 33.544.555.56 vdd(v) vol(v) at lio=8ma 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 3 3.5 4 4.5 5 5.5 6 vdd(v) vol(v) at lio=20m a 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-2m a 0 0.2 0.4 0.6 0.8 1 1.2 3 3.5 4 4.5 5 5.5 6 vdd(v) vdd-voh(v) at iio=-5ma ST7261 65/77 i/o port pin characteristics (contd) figure 51. typical v dd -v oh vs. v dd (high sink port) 11.9 control pin characteristics 11.9.1 asynchronous reset pin subject to general operating conditions for v dd , f cp , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v, not tested in production. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the i io current sunk must always respect the absolute maximum rating specified in section 11.2 and the sum of i io (i/ o ports and control pins) must not exceed i vss . 5. the r on pull-up equivalent resistor is based on a resistive transistor (corresponding i on current characteristics de- scribed in figure 52 ). this data is based on characterization results, not tested in production. 6. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. 0 0.02 0.04 0.06 0.08 0.1 33.544.555.56 vdd(v) vdd-voh (v) at lio=-2ma 0 0.05 0.1 0.15 0.2 0.25 3456 vdd(v) vdd-voh (v) at iio=-5m a symbol parameter conditions min typ 1) max unit v ih input high level voltage 0.7xv dd v dd v v il input low voltage v ss 0.3xv dd v v hys schmitt trigger voltage hysteresis 3) 400 mv v ol output low level voltage 4) (see figure 53 , figure 54 ) v dd =5v i io =5ma 1 v i io =2ma 0.4 r on weak pull-up equivalent resistor 5) v in = v ss 80 160 280 k w t w(rstl)out generated reset pulse duration external pin or internal reset sources 6 30 1/f sfosc m s t h(rstl)in external reset pulse hold time 6) 10 m s ST7261 66/77 control pin characteristics (contd) figure 52. typical i on vs. v dd with v in =v ss figure 53. typical v ol at v dd =5v (reset ) figure 54. typical v ol vs. v dd (reset ) 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 3 3.5 4 4.5 5 5.5 6 vdd (v) ion (ma) 0.0 0.2 0.4 0.6 0.8 1.0 0123456789 i io (ma) v ol (v) 0 0.05 0.1 0.15 0.2 0.25 0.3 33.544.555.566.5 v dd (v) v ol (v) at i io =2ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 33.544.555.566.5 v dd (v) v ol (v) at i io =5ma ST7261 67/77 11.10 communication interface characteristics 11.10.1 usb - universal bus interface (operating conditions t a = 0 to +70c, v dd = 4.0 to 5.25v unless otherwise specified) note 1: rl is the load connected on the usb drivers. note 2: all the voltages are measured from the local ground potential. note 3: not tested in production, guaranteed by design. note 4: to improve emc performance (noise immunity), it is recommended to connect a 100nf capacitor to the usbvcc pin. figure 55. usb: data signal rise and fall time table 17. usb: low-speed electrical characteristics note 1: measured from 10% to 90% of the data signal. for more detailed informations, please refer to chapter 7 (elec- trical) of the usb specification (version 1.1). usb dc electrical characteristics parameter symbol conditions min. max. unit differential input sensitivity vdi i(d+, d-) 0.2 3) v differential common mode range vcm includes vdi range 0.8 3) 2.5 3) v single ended receiver threshold vse 0.8 3) 2.0 3) v static output low vol rl of 1.5k ohms to 3.6v 0.3 v static output high voh rl of 15k ohms to v ss 2.8 3.6 v usbvcc: voltage level 4) usbv v dd =5v 3.00 3.60 v differential data lines v ss tf tr crossover points vcrs parameter symbol conditions min max unit driver characteristics: rise time tr note 1,cl=50 pf 75 ns note 1, cl=600 pf 300 ns fall time tf note 1, cl=50 pf 75 ns note 1, cl=600 pf 300 ns rise/ fall time matching trfm tr/tf 80 120 % output signal crossover voltage vcrs 1.3 2.0 v ST7261 68/77 12 package mechanical data figure 56. 20-pin plastic small outline package, 300-mil width figure 57. 20-pin plastic dual in-line package, 300-mil width dim. mm inches min typ max min typ max a 2.35 2.65 0.0926 0.1043 a1 0.10 0.0040 b 0.33 0.51 0.0130 0.0200 c 0.32 0.0125 d 4.98 13.00 0.1961 0.5118 e 7.40 7.60 0.2914 0.2992 e 1.27 0.050 h 10.01 10.64 0.394 0.419 h 0.25 0.74 0.010 0.029 k 0 8 0 8 l 0.41 1.27 0.016 0.050 g 0.10 0.004 number of pins n20 so20 dim. mm inches min typ max min typ max a 5.33 0.210 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 24.89 26.92 0.980 1.060 e 2.54 0.100 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 20 pdip20 ST7261 69/77 13 device configuration and ordering information each device is available for production in rom versions. the user programmable version (flash) is supported by the st72f623f2. the rom devices are factory-configured. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. 13.1 option byte the option byte allows the hardware configuration of the microcontroller to be selected. the option byte has no address in the memory map and can be accessed only in programming mode using a standard st7 programming tool. option byte bit 7:6 = reserved. bit 5 = wdgsw hardware or software watchdog this option bit selects the watchdog type. 0: hardware enabled 1: software enabled bit 4 = reserved bit 3 = lvd low voltage detector selection this option bit selects the lvd. 0: lvd enabled 1: lvd disabled note: when the usb interface is used, it is recom- mended to activate the lvd. bit 2= reserved. bit 1 = osc12/6 oscillator selection this option bit selects the clock divider used to drive the usb interface at 6mhz. 0: 6 mhz oscillator (no divider for usb) 1: 12 mhz oscillator (2 divider for usb) bit 0 = fmp_r read out protection this option bit allows the protection of the software contents against piracy (program or data). when the protection is activated, read/write access is prevented by hardware. if the protection is deacti- vated, the memory is erased first. 0: read-out protection enabled 1: read-out protection disabled 70 11 wdg sw - lvd - osc 12/6 fmp_ r ST7261 70/77 13.2 device ordering information table 18. supported part numbers part number program memory (bytes) ram (bytes) package ST72611f1b1 4k rom 256 pdip20 ST72611f1m1 so20 contact st sales office for product availability ST7261 71/77 13.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site: ? http//mcu.st.com. tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools three types of development tool are offered by st see table 19 and table 20 for more details. table 19. stmicroelectronics tools features note : 1. in-circuit programming (icp) interface for flash devices. table 20. dedicated stmicroelectronics development tools note : 1. add suffix /eu or /us for the power supply for your region. note: the flash version of the ST7261 is supported by the st72f623f2. in-circuit emulation programming capability 1) software included st7 emulator yes, powerful emulation features including trace/ logic analyzer no st7 cd rom with: C st7 assembly toolchain C stvd7 powerful source level debugger for win 3.1, win 9x and nt C c compiler demo versions C windows programming tools for win 3.1, win 9x and nt st7 programming board no yes (all packages) supported products evaluation board st7 emulator st7 programming board active probe & target emulation board ST7261 st7mdtuls-eval st7mdtu2-emu2b st7mdtu2-epb 1) st7mdtu2-dbe2b ST7261 72/77 ST7261 microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference/rom code* : . . . . . . . . . . . . . . . . . . *the rom code name is assigned by stmicroelectronics. rom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/package (check only one option): conditioning (check only one option): special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ " authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character count: s020 (8 char. max) : _ _ _ _ _ _ _ _ dip20 (10 char. max) : _ _ _ _ _ _ _ _ _ _ watchdog selection: [ ] software activation [ ] hardware activation lvd reset: [ ] disabled [ ] enabled oscillator selection: [ ] 6 mhz. [ ] 12 mhz. readout protection: [ ] enabled [ ] disabled date . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . ----------------------------- rom device: ----------------------------- | | ------------------------------------- 4k ------------------------------------- sdip20: | [ ] ST72611f1b1 so20: | [ ] ST72611f1m1 ----------------------------- die form: ----------------------------- | | ------------------------------------- 4k ------------------------------------- 20-pin: | [ ] ------------------------------------------------------- packaged product: ------------------------------------------------------- | | ------------------------------------------------------------ die product (dice tested at 25c only) ------------------------------------------------------------ [ ] tape & reel (so package only) | [ ] tape & reel [ ] tube | [ ] inked wafer | [ ] sawn wafer on sticky foil ST7261 73/77 14 known limitations 14.1 unexpected reset fetch if an interrupt request occurs while a "pop cc" in- struction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a "pop cc" instruction must always be preceded by a "sim" instruction. 14.2 lvd reset on v dd brownout if v dd drops into the range 2.4v to 0.5v but does not go below 0.5v, the lvd reset is not held low and follows the level of v dd . in this case, usbvcc may not be correctly activated. at power-on, v dd must rise monotonously to en- sure the lvd reset stays low until the vit+ thresh- old is crossed (see figure 58 ) to reset the device correctly and recover normal operation, the v dd must be brought below 0.5v. the lvd reset functions correctly if v dd drops into the range v it- to 2.4v or if v dd drops below 0.5v. figure 58. lvd reset on v dd brownout v it- 2.4 0.5 v it+ reset uncorrect function ST7261 74/77 14.3 st7 application notes identification description example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communicating between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripheral registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 permanent magnet dc motor drive. an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 using the st7 spi to emulate a 16-bit slave an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer product evaluation an 910 performance benchmarking an 990 st7 benefits versus industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 application to st72f264 product optimization ST7261 75/77 an 982 using st7 with ceramic renator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1477 emulated data eeprom with xflash memory an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscil- lator programming and tools an 978 key features of the stvd7 st7 visual debug package an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bridge using the ST72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug a st72324 target application an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus identification description ST7261 76/77 15 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 2.0 removed references to flash and fastrom devices added nested interrupt feature updated section 11 on page 50 and section 13 on page 69 added section 14 on page 73 added known limitations on page 73 nov 02 ST7261 77/77 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com |
Price & Availability of ST7261
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |